Setup time in Physical Design
Setup time : The arrival time of a signal which is launched at launch flop should be less than the required time for the capture flop to receive it correctly arrival time < required time . components of arrival time : clk to q delay ( Tcq) data path delay ( Tcomb) setup time of a flop ( Tsetup ) components of required time : clock period ( Tclock ) Tcq : This data will be obtained from the library based on input transition on the clock pin and output pin load Tsetup : This value will be obtained from the library depends on the input data transition and clock pin transition and the delay to take the loop back inside the flop Tclock : This value is defined before the project ( wont change ) Tcomb : This is the value the designers will have control to optimize and modify to meet the setup timing Tcq+Tcomb+Tsetup < Tclock But in timing reports the setup time of flop always will be removed from required time , so the timing equation turns out ...